Multiplexers and Demultiplexers

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In the previous exercise, you constructed a 4-bit prime number detector by deriving a complete Sum of Products (SOP) expression and simplifying it via Boolean algebra. While mathematically rigorous, implementing such high-variable logic with individual gates often leads to high component counts and complex wiring on a breadboard.

1) Multiplexers (MUX)

An n-bit multiplexer has the following function: Given 2^n 1-bit inputs and one n-bit "select" input, it provides one 1-bit output. If the n-bit input is x, then the output is equal to the x^{th} 1-bit input. More simply, a multiplexer takes several inputs and a selection number, then forwards the input at that position to the output.

The most fundamental unit is the 2:1 Multiplexer. It features two data inputs (a and b) and one select bit (s).

Block diagrams of 2-to-1, 4-to-1, and 8-to-1 multiplexers showing data inputs, select lines, and a single output.
Standard Multiplexer Block Diagrams.

The operation of a 2:1 MUX is defined by the following Boolean equation: o = (s' \cdot a) + (s \cdot b)

s (Select) a (Input 0) b (Input 1) o (Output)
L L L L
L L H L
L H L H
L H H H
H L L L
H L H H
H H L L
H H H H
Gate-level circuit of a 2:1 multiplexer using two AND gates, one NOT gate, and one OR gate.
Internal logic of a 2:1 Multiplexer.

Activity: Building a 2:1 Multiplexer

To understand the internal logic of a data selector, you will build a 2:1 MUX using discrete logic gates.

Components needed:

  • 1x Breadboard
  • 1x 74LS08 (Quad 2-input AND gate)
  • 1x 74LS32 (Quad 2-input OR gate)
  • 1x 74LS04 (Hex Inverter/NOT gate)
  • LEDs and 330\Omega resistors for output visualization
  • Jumper wires and power supply

Step-by-step design guide:

  1. Power the ICs: Place the 74LS04, 74LS08, and 74LS32 on your breadboard. Connect Pin 14 of each to VCC (5V) and Pin 7 to GND.
  2. Invert the Select Line: Connect your select signal (s) to the input of a NOT gate (Pin 1 of 74LS04). The output (Pin 2) is now s'.
  3. Implement the AND terms: * Connect s' (from Pin 2 of 74LS04) and input a to the first AND gate (Pins 1 and 2 of 74LS08).
    • Connect the direct select signal s and input b to the second AND gate (Pins 4 and 5 of 74LS08).
  4. Final Summation: Connect the outputs of the two AND gates (Pins 3 and 6 of 74LS08) to the inputs of an OR gate (Pins 1 and 2 of 74LS32).
  5. Verify: Connect the OR gate output (Pin 3 of 74LS32) to an LED. Test all four combinations of a and b for both s=0 and s=1 to match the truth table.
Complete breadboard implementation of a 2:1 Multiplexer using 74-series logic gates.
Complete Breadboard Design for 2:1 Multiplexer.

Multiplexers are often described as 'universal logic modules.' If you fix the data inputs a and b to specific logic levels (0 or 1), a 2:1 MUX can mimic basic gates. To make a 2:1 MUX behave exactly like an inverter (NOT gate) where the select bit s is the input, what should a and b be tied to?

To build an 8-to-1 multiplexer using only 2-to-1 multiplexers as building blocks, how many 2-to-1 MUX modules would you need in total? (Hint: Think in levels or a 'tree' structure).

2) Demultiplexers (DEMUX)

A demultiplexer does the exact opposite of a multiplexer. Given one n-bit select input and one 1-bit data input, it provides 2^n 1-bit outputs. If the n-bit select input is x, then the x^{th} output is equal to the 1-bit data input, and all other outputs are LOW.

Block diagrams of 1-to-2, 1-to-4, and 1-to-8 demultiplexers showing data inputs, select lines, and multiple outputs.
Standard Demultiplexer Block Diagrams.

Hence, we can construct the following truth table for a 1:2 demultiplexer:

s (Select) i (Input) a (Output 0) b (Output 1)
L L L L
L H H L
H L L L
H H L H
Block diagram and gate-level circuit of a 1-to-2 demultiplexer showing one data input, one select line, and two outputs.
1:2 Demultiplexer Architecture.

Demultiplexers and Decoders are closely related. If the 1-bit data input i of a 1:2 DEMUX is permanently tied to HIGH (1), what common digital component does the circuit essentially become?

In a memory system, if you need to route a single 'Write' pulse to one of 16 different memory registers, what is the minimum number of select bits (s lines) required for the Demultiplexer?

3) Partitioning for the Prime Detector

A powerful application of multiplexers is "function implementation by partitioning." We can implement the 4-bit prime detector by using the Most Significant Bit (MSB), x_8, as the select pin (s) for a 2:1 MUX. This effectively splits the 16-row truth table into two 8-row sub-problems. When x_8 = 0, the MUX selects the logic for numbers 0–7. When x_8 = 1, it selects the logic for numbers 8–15.

Partition 1 (x_8 = 0): Numbers 0-7 The prime numbers in this range are 2, 3, 5, and 7.

x_4 x_2 x_1 Output (y)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Partition 2 (x_8 = 1): Numbers 8-15 The prime numbers in this range are 11 (1011_2) and 13 (1101_2).

x_4 x_2 x_1 Output (y)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 (Decimal 11)
1 0 0 0
1 0 1 1 (Decimal 13)
1 1 0 0
1 1 1 0

Activity: 4-Bit Prime Detector Integration

Let's design the same 4-bit prime number detector you designed in the previous exercise using MULTIPLEXER that you just designed, and the 3-bit prime number detector along with some more gates.

Gate diagram of the prime number detector with MUX
Prime detector with MUX

Components needed:

  • Your existing 3-bit prime detector circuit (from Partition 1)
  • New logic gates for Partition 2 (1x 74LS86 XOR gate and 1x 74LS08 AND gate to detect 11 and 13)
  • The 2:1 MUX circuit built in the previous activity
  • Four input switches (x_8, x_4, x_2, x_1)

Step-by-step design guide:

  1. Prepare Logic Outputs:
    • Ensure your 3-bit prime detector output (from previous module) is ready to serve as input a for the MUX.
    • Implement logic for Partition 2: The unsimplified expression for 11 and 13 is y = x_4'x_2x_1 + x_4x_2'x_1, which simplifies to y = (x_4 \oplus x_2) \cdot x_1. This uses an XOR gate and an AND gate to detect 1011 and 1101 when the MSB is assumed to be 1. This output will serve as input b for the MUX.
  2. Connect to MUX: * Wire the output of Partition 1 to MUX Input a.
    • Wire the output of Partition 2 to MUX Input b.
  3. Assign the Select Line: Use the x_8 switch as the select bit (s) for the MUX.
  4. Final Test: Switch through all 16 binary inputs. The final LED at the MUX output should only light up for primes: 2, 3, 5, 7, 11, and 13.
Breadboard showing the 3-bit prime detector integrated with partition logic and a 2:1 MUX to form a 4-bit detector.
Complete Breadboard Design for MUX-Integrated 4-Bit Prime Detector.

Derive the unsimplified SOP expression for the primes in Partition 2 (11 and 13) using only the variables x_4, x_2, and x_1. Write your answer using prime notation for NOT (e.g., x4'x2x1 + x4x2'x1).

Construct the partitioned prime detector on your breadboard. Integrate your existing 3-bit prime logic and the new logic for Partition 2 using the MUX as the bridge. Upload a clear photo of your breadboard and a short video verifying the circuit correctly identifies prime numbers 7 (0111_2) and 13 (1101_2).
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Next, we will build an 7 segment display decoder from scratch using the concepts learnt in the module.