Binary to 7-segment Display Decoder
In this project, you will be designing a circuit you will use fairly often in this course---a binary to 7-segment display decoder.
Because of the complexity and tedium of building a complete version of this circuit (going from 0 to 9 (or 0 to F for hexadecimal)), we will be building a simplified version. This one will only decode numbers from 0 to 5, which will be useful for building a clock, since minutes and seconds only go up to 59.
Here, we will introduce some new notation: X. In a truth table, this denotes a value which does not matter to the functioning of the circuit. In particular, we will be using this for input numbers greater than 5.
For this project, we will be creating separate circuits with each segment of the 7-segment display, since they are all somewhat independent of each other. First, let us name the segments. Typically, each of the seven segments are labelled one of a,b,c,d,e,f,g. In most single 7-segment displays, there is also a decimal point, which we will ignore for this circuit. In the diagram below, the decimal point is labelled DP.
Now, let us construct a truth table for this circuit.
| x | x_4 | x_2 | x_1 | a | b | c | d | e | f | g | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | L | L | L | H | H | H | H | H | H | L | ||
| 1 | L | L | H | L | H | H | L | L | L | L | ||
| 2 | L | H | L | H | H | L | H | H | L | H | ||
| 3 | L | H | H | H | H | H | H | L | L | H | ||
| 4 | H | L | L | L | H | H | L | L | H | H | ||
| 5 | H | L | H | H | L | H | H | L | H | H | ||
| 6 | H | H | L | X | X | X | X | X | X | X | ||
| 7 | H | H | H | X | X | X | X | X | X | X |
Use all the techniques you have learnt to create a this circuit.
Solution
To start with, notice that a\equiv d. This means that we only need to design circuits for six of the segments. So, let us take a look at them one at a time.
a)
| x_4 | x_2 | x_1 | a | |
|---|---|---|---|---|
| L | L | L | H | |
| L | L | H | L | |
| L | H | L | H | |
| L | H | H | H | |
| H | L | L | L | |
| H | L | H | H | |
| H | H | L | X | |
| H | H | H | X |
For this one, we can see that there are four rows for which a=H, and hence two rows for which a=L. Because of this, we can come up with an expression which is LOW only for those two rows (similar to what we did in the previous section)
- \bar a \Leftarrow x_1 \cdot \bar x_2 \cdot \bar x_4
- \bar a \Leftarrow x_4 \cdot \bar x_2 \cdot \bar x_1
Inverting each of these and connecting them with an AND:
- a \equiv \overline{x_1 \cdot \bar x_2 \cdot \bar x_4} \cdot \overline{x_4 \cdot \bar x_2 \cdot \bar x_1}
Simplifying using de Morgan's law:
- a \equiv \overline{(x_1 \cdot \bar x_2 \cdot \bar x_4) + (x_4 \cdot \bar x_2 \cdot \bar x_1)}
By distributivity:
- a \equiv \overline{\bar x_2 \cdot (x_1 \cdot \bar x_4 + x_4 \cdot \bar x_1)}
Take note of the expression x_1 \bar x_4 + \bar x_1 x_4; we have been using a similar expression.
This is identical to the definition of \oplus. Thus:
- a \equiv \overline{\bar x_2 \cdot (x_1 \oplus x_4)}
By de Morgan's law:
- a \equiv x_2 + \overline{x_1 \oplus x_4}
This is about as simplified we are going to be able to get it, so we can stop here. This expression will use three gates—one XOR gate, one OR gate, and one NOT gate.
b)
| x_4 | x_2 | x_1 | b | |
|---|---|---|---|---|
| L | L | L | H | |
| L | L | H | H | |
| L | H | L | H | |
| L | H | H | H | |
| H | L | L | H | |
| H | L | H | L | |
| H | H | L | X | |
| H | H | H | X |
Here we only have one row where b \equiv L. From this we get:
- \bar b \equiv x_4 \cdot \bar x_2 \cdot x_1
We cannot simplify it further. Using de Morgan's law gets us the following:
- b \equiv \bar x_4 + x_2 + \bar x_1
This highlights one problem with this approach: When there are don't care (X) conditions, this method does not yield the minimal expression. Right now, there are two don't care conditions, and so there are four possible expressions, each for a different combination of values of X.
In this case, we can find the minimal expression with brute force. This will not work, however, for truth tables with more X conditions.
In this case, there is at least one minimal solution that is constructible using only two logic gates from AND, OR, XOR, NAND, NOR, NOT (Note that they need not be two different gates)
c)
This row has a solution with one gate.
Hint
One of the three inputs does not matter here.
d)
Hint
This question is just checking if you have been paying attention so far. This should be trivial if you have been.
e)
Here, there is a solution with two logic gates.
f)
This will require two logic gates.
g)
g can be expressed using only one logic gate.
Minimised Expressions
- a \equiv d \equiv x_2 + \overline{x_1 \oplus x_4}
- b \equiv \overline{(x_1 \cdot x_4)}
- c \equiv x_1 + \bar x_2
- e \equiv \overline{(x_1 + x_4)}
- f \equiv \bar x_2 + x_4
- g \equiv x_2 \oplus x_4